One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cho K. | - |
dc.contributor.author | Park J. | - |
dc.contributor.author | Oh T.W. | - |
dc.contributor.author | Jung S.-O. | - |
dc.date.accessioned | 2023-04-21T01:40:15Z | - |
dc.date.available | 2023-04-21T01:40:15Z | - |
dc.date.issued | 2020-05 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.issn | 1558-0806 | - |
dc.identifier.uri | https://yscholarhub.yonsei.ac.kr/handle/2021.sw.yonsei/6603 | - |
dc.description.abstract | This paper presents a one-sided Schmitt-Trigger-based 9T static random access memory cell with low energy consumption and high read stability, write ability, and hold stability yields in a bit-interleaving structure without write-back scheme. The proposed Schmitt-Trigger-based 9T static random access memory cell obtains a high read stability yield by using a one-sided Schmitt-Trigger inverter with a single bit-line structure. In addition, the write ability yield is improved by applying selective power gating and a Schmitt-Trigger inverter write assist technique that controls the trip voltage of the Schmitt-Trigger inverter. The proposed Schmitt-Trigger-based 9T static random access memory cell has 0.79, 0.77, and 0.79 times the area, and consumes 0.31, 0.68, and 0.90 times the energy of Chang's 10T, the Schmitt-Trigger-based 10T, and MH's 9T static random access memory cells, respectively, based on 22-nm FinFET technology. © 2004-2012 IEEE. | - |
dc.format.extent | 11 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation | - |
dc.type | Article | - |
dc.publisher.location | 미국 | - |
dc.identifier.doi | 10.1109/TCSI.2020.2964903 | - |
dc.identifier.scopusid | 2-s2.0-85084405331 | - |
dc.identifier.wosid | 000531328700013 | - |
dc.identifier.bibliographicCitation | IEEE Transactions on Circuits and Systems I: Regular Papers, v.67, no.5, pp 1551 - 1561 | - |
dc.citation.title | IEEE Transactions on Circuits and Systems I: Regular Papers | - |
dc.citation.volume | 67 | - |
dc.citation.number | 5 | - |
dc.citation.startPage | 1551 | - |
dc.citation.endPage | 1561 | - |
dc.type.docType | Article | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | Cells | - |
dc.subject.keywordPlus | Cytology | - |
dc.subject.keywordPlus | Electric inverters | - |
dc.subject.keywordPlus | Energy utilization | - |
dc.subject.keywordPlus | Memory architecture | - |
dc.subject.keywordPlus | Semiconductor storage | - |
dc.subject.keywordPlus | Trigger circuits | - |
dc.subject.keywordPlus | Bit-interleaving | - |
dc.subject.keywordPlus | Low energy consumption | - |
dc.subject.keywordPlus | Near thresholds | - |
dc.subject.keywordPlus | Power gatings | - |
dc.subject.keywordPlus | Read stability | - |
dc.subject.keywordPlus | Schmitt trigger | - |
dc.subject.keywordPlus | Single bit lines | - |
dc.subject.keywordPlus | Static random access memory | - |
dc.subject.keywordPlus | Static random access storage | - |
dc.subject.keywordAuthor | Bit interleaving | - |
dc.subject.keywordAuthor | low energy | - |
dc.subject.keywordAuthor | near-Threshold | - |
dc.subject.keywordAuthor | Schmitt-Trigger | - |
dc.subject.keywordAuthor | static random access memory (SRAM) | - |
Items in Scholar Hub are protected by copyright, with all rights reserved, unless otherwise indicated.
Yonsei University 50 Yonsei-ro Seodaemun-gu, Seoul, 03722, Republic of Korea1599-1885
© 2021 YONSEI UNIV. ALL RIGHTS RESERVED.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.