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A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications

Authors
김세건Cho, KeonheeBaek, KyeongrimKim, HyunjunBae, YounmeeKim, MijungSeo, DongwookBaeck, SangyeopLee, SungjaeJung, Seong-Ook
Issue Date
11-Jun-2023
URI
https://yscholarhub.yonsei.ac.kr/handle/2021.sw.yonsei/22909
DOI
10.23919/vlsitechnologyandcir57934.2023.10185239
Conference Name
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
Place
일본
Kyoto, Japan
Conference Date
2023-06-11 ~ 2023-06-16
metadata.conference.dc.citation.conferenceName
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
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College of Engineering > 공과대학 전기전자공학부 > 공과대학 전기전자공학과 > 3. Conference Papers

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