SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling
- Authors
- KEONHEE CHO; HEE KYUNG CHOI; INJUN JUNG; 오지상; TAE WOO OH; KIRYONG KIM; Giseok Kim; SEONGOOK JUNG; Taemin Choi; Changsu Sim; Taejoong Song
- Issue Date
- Apr-2022
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Energy efficiency; near-threshold operation; static random access memory (SRAM); SRAM write assist circuit
- Citation
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.4, pp 1,039 - 1,048
- Journal Title
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- Volume
- 57
- Number
- 4
- Start Page
- 1,039
- End Page
- 1,048
- URI
- https://yscholarhub.yonsei.ac.kr/handle/2021.sw.yonsei/6334
- DOI
- 10.1109/JSSC.2021.3138785
- ISSN
- 0018-9200
- Abstract
- In this article, we present static random access memory (SRAM) write- and performance-assist cells (W- and P-ACs, respectively) that can effectively resolve the degradation in writeability and performance due to the increase in interconnect resistance with technology scaling. The proposed W- and P-ACs have bit-cell compatible layouts, and thus, they can be inserted into a bit-cell array without white space. Given that bit-line (BL) and BL-bar (BLB) are driven in parallel by the write driver (WD) and proposed W-AC, the effective BL resistance $(R_{{BL}}$ ) is reduced. This, in turn, leads to an improvement in writeability. In addition, the proposed P-AC accelerates word-line (WL) by sensing WL rising voltage and, thus, improves the read access time on the bit-cell located far from the WL driver. To measure the interconnect resistance effects, 32-kb SRAM macros with poly resistors were fabricated on 28-nm CMOS technology. The proposed W-AC achieves 100% writeability yield not only in the 3-nm resistance model but also in the sub-3-nm resistance model, while the writeability yield of the conventional scheme with a single WD decreased to 2.3 sigma in the 3-nm resistance model. The proposed P-AC reduced the read access time by 28% compared with that of the conventional scheme with a single WL driver in the 3-nm resistance model.
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Collections - College of Engineering > Electrical and Electronic Engineering > 1. Journal Articles
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