Local Bit-Line SRAM Architecture With Data-Aware Power-Gating Write Assist
- Authors
- Oh Tae Woo; Park Juhyun; Kim Tae Hyun; Cho Keonhee; Jung Seong-Ook
- Issue Date
- Jan-2023
- Publisher
- Institute of Electrical and Electronics Engineers
- Citation
- IEEE Transactions on Circuits and Systems II: Express Briefs, v.70, no.1, pp 306 - 310
- Pages
- 5
- Journal Title
- IEEE Transactions on Circuits and Systems II: Express Briefs
- Volume
- 70
- Number
- 1
- Start Page
- 306
- End Page
- 310
- URI
- https://yscholarhub.yonsei.ac.kr/handle/2021.sw.yonsei/6419
- ISSN
- 1549-7747
1558-3791
- Abstract
- In this brief, a local bit-line (LBL) SRAM with dataaware power-gating write assist is proposed for near-threshold operation. The proposed SRAM achieves high read stability and write ability by adopting LBL architecture and power-gating transistors, respectively. Depending on the input data, one of the power-gating transistors is adaptively cut off, which eliminates the write disturbance from the power supply. Thus, reliable write operation can be performed. The proposed SRAM achieves a read stability yield of 5.12 sigma, write ability yield of 7.26s, and consumes 0.21 pJ energy/operation with 58% shorter read delay and 33% smaller area per bit than the 12T SRAM at a supply voltage of 0.4 V in a 22-nm FinFET process.
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Collections - College of Engineering > Electrical and Electronic Engineering > 1. Journal Articles
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