SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation
- Authors
- Cho, Keonhee; Park, Juhyun; Kim, Kiryong; Oh, Tae Woo; Jung, Seong-Ook
- Issue Date
- Mar-2022
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Transistors; SRAM cells; Logic gates; Transient analysis; Delays; Circuits and systems; Circuit stability; Energy efficiency; near-threshold operation; static random access memory (SRAM); SRAM write assist circuit
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.69, no.3, pp 1567 - 1571
- Pages
- 5
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
- Volume
- 69
- Number
- 3
- Start Page
- 1567
- End Page
- 1571
- URI
- https://yscholarhub.yonsei.ac.kr/handle/2021.sw.yonsei/6573
- DOI
- 10.1109/TCSII.2021.3103916
- ISSN
- 1549-7747
1558-3791
- Abstract
- This brief presents SRAM write assist circuit using cell supply voltage self-collapse with bitline charge sharing (SC-BCS) that can lower the minimum operating voltage to the near-threshold voltage (V-th) region while consuming a minimal write energy. The proposed SC-BCS improves the write-ability by utilizing the cell supply voltage (CVDD) self-collapse and the feedback operation through the detection of write failure. Because the amount of CVDD collapse is regulated automatically depending on the write-ability of the selected cell, the write energy of the proposed SC-BCS is effectively reduced. The proposed SC-BCS can achieve a 5 sigma write-ability yield with a smaller delay overhead than gate-modulated self-collapse and self-collapse write assists in the near-V-th region. In addition, the proposed SC-BCS consumes the lowest write energy with minimal delay overhead or without any delay overhead compared with the strong-bias transient CVDD collapse and pulsed-pMOS transient CVDD collapse. The measurement result of the test chip fabricated using 65-nm CMOS technology indicates that the proposed SC-BCS can operate without any failure up to 0.36 V consuming write power 12.6 mu W/MHz.
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Collections - College of Engineering > Electrical and Electronic Engineering > 1. Journal Articles
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